Multiplication circuit

Abstract

Abstract PURPOSE:To realize the high-speed multiplication processing by using one of four multipliers for basic word length to perform the multiplication of the basic word length and then using all of these four multipliers for multiplication of the double word length respectively. CONSTITUTION:An adder 50 is used only for multiplication of the 8-bite data and serves as a 3-input addition circuit which adds the partial products P1-P4 received from multiplication units 1-4 respectively with proper digit matching. The output of the 3-input adder 50 is set at registers 61-63 respectively. At the same time, a partial product P4L is set as it is at a register 64. The output selection circuits 81 and 82 select the output of the unit 1 with the (4X4 bytes)- multiplication and then the outputs of registers 61-64 with the (8X8 bytes)- multiplication. While the output selection circuits 71 and 72 selects and reads out both higher and lower level 8 bytes respectively of 16 bytes of the (8X8 bytes)-multiplication. The multiplication result of the unit 1 is selected by both circuits 81 and 82 with multiplication of the basic word length and then delivered directly. Thus the time needed for the multiplication processing can be shortened.

Inventors

• 👤 Yuji Yoshida
• 👤 Shigeharu Matsuzaki

Bibliographic Details