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JPS642372A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of mes fet

Assignee: Toshiba Corp
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Filing: 1987-06-25
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Granted: —
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Expires: 2007-06-25
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Abstract

Abstract PURPOSE: To prevent the generation of positioning displacement by a positioning process by determining the position of a gate electrode by self-alignment. CONSTITUTION: The surface of a GaAs substrate 1 to which an operating layer 11 is formed is coated with first thin-film Si 3 N 4 2, second thin-film SiO 2 3 and third thin-film Al 4, and a photo-resist layer 5 is applied and a resist pattern 6 is shaped. A photo-resist 7 is applied, the resist 7 is etched and etching is completed when the film 4 is exposed to a stepped section (a). The films 4, 3 are side-etched, and the size (b), (c) of the films 4, 3 is controlled so that (c) is made larger than (b). The film 2 is etched, and the layer, 7 is removed. The substrate 1 exposed through an opening formed by getting rid of the film 2 is etched to shape a recess 8, and a metal as a gate electrode 9 is evaporated. A photo-resist is applied, and etched from the top section of the photo-resist and the resist 10 is left only in the air gap section 8. The excess films 4, 3 are taken off under the state, and the resist 10 is melted and removed, thus acquiring offset gate structure. COPYRIGHT: (C)1989,JPO&Japio

Inventors

  • 👤 Yoshinori Yamada

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 16:44
CPC Classifications
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