← Back to Patent Explorer
JPS6414934A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device and film carrier tape

Assignee: Toshiba Corp
•
Filing: 1987-07-09
•
Granted: —
•
Expires: 2007-07-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To display the high speed performance of a chip in correspondence with the increase in number of input terminals and the implementation of high density, by forming a feed through wiring and a straight line shape without bending in a wire, which is connected to a signal input terminal. CONSTITUTION:In a TAB board, a copper foil is stuck on a flexible long resin film 1, and a signal transmission wire 2, conductor wire 3 and a ground conductor wire 3 and a rear surface ground conductor wire 8 are formed. The ground conductor wire 3 and the rear surface ground conductor wire 8 are connected with a plurality of through hole conductors 5, and a terminating potential is provided. An integrated circuit chip 7 and the signal transmission wire 2 are connected through a protruding electrode 6. The protruding electrode 6 is formed by applying Au plating 62 of a barrier metal layer 61 comprising Ti-Ni-Pd and the like, which is formed on an Al bonding pad 9. The through hole conductors 4 and 5 are formed by Cu plating. Sn plating is applied at the connecting surface with the protruding electrode. The lead-out part of the signal transmission wire 2 is conencted to a terminating potential VTT through a terminating resistor R. The combination of the signal transmission wire 2 and the ground conductors 3 and 8 is adjusted to the specified characteristic impedance. The arranging direction of the signal transmission wire is slightly inclined with respect to the arrangement of an element.

Inventors

  • 👤 Kazuyoshi Saito
  • 👤 Tomoaki Takubo
  • 👤 Toshio Sudo

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 11:47
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS5831566A Cited
JPS6046040A Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag