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JPS6399549A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory integrated circuit device

Assignee: NEC Corp
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Filing: 1986-10-16
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Granted: —
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Expires: 2006-10-16
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Abstract

Abstract PURPOSE: To make it possible to indicate addresses in a memory cell in a readily understandable way, by arranging contacts, which are formed on wirings arranged in the neighborhood of memory cell array parts, at every specified number of bits in the memory cell array parts, and differentiating the number of holes or their shapes. CONSTITUTION:In a memory integrated circuit device, memory cell array parts 3 are formed in a wide area at the central part of a chip 5. An X decoder part 4 is formed at a part of the array parts 3. On one side of the memory cell array part 3, a side power-source wiring 1 is extended. The side power- source wiring 1 is connected to diffused layers 2 and the like, which are extended to the memory cell array part 3 and the like through contacts 6, which are arranged on the side power-source wiring 1. The contacts 6 are arranged for every specified number of bits in a memory cell columns, which are formed in the memory cell array part 3. The numbers of the contacts 6 are sequentially changed as 1, 2, 3.... Therefore, the addresses of memory cells can be readily detected only by confirming the contacts.

Inventors

  • 👤 Hiroshi Furuta
  • 👤 博伺 古田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 03:12
CPC Classifications
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