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JPS6364698A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory device

Assignee: Fujitsu VLSI Ltd
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Filing: 1986-09-04
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Granted: —
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Expires: 2006-09-04
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Abstract

Abstract PURPOSE:To facilitate the realization of a multibit constitution by transmitting count information as an address signal to a column decoder. CONSTITUTION:A column address is set to a nibble counter 1 in a normal cycle. A setting action is made by a clock phi setting the column address to an address buffer 2. When a nibble clock phiNBC is impressed, counting up is made. In a next nible cycle, an address for the counter 1 is pulled out to operate the column decoder. After the buffer 2 amplifies the address for the counter 1, said address is transmitted to the column decoder or a serial decoder. After the address is outputted, the counter 1 is counted up by the clock phiNBC.

Inventors

  • 👤 Masao Nakano
  • 👤 正夫 中野
  • 👤 Hirohiko Mochizuki
  • 👤 望月 裕彦
  • 👤 Takeshi Ohira
  • 👤 大平 壮
  • 👤 Yukinori Kodama
  • 👤 幸徳 児玉
  • 👤 Hidenori Nomura
  • 👤 野村 英則

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 06:55
CPC Classifications
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Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS61170994A Cited

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