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JPS63294084A Expired / Lapsed JP ⏱️ 0.0 years remaining

Data input and output system for picture frame memory

Assignee: Fuji Electric Co Ltd
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Filing: 1987-05-27
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Granted: —
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Expires: 2007-05-27
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Abstract

Abstract PURPOSE:To easily process picture information between adjacent picture elements by providing a mode discriminating means and a field discriminating means and inputting and outputting the picture data of an interlace scanning system or a non-interlace scanning system. CONSTITUTION:An FF4 latches a scanning mode switching signal EX at the timing of a frame start signal FS and controls the change over of switches S1-S3 by a Q output. A field counter 5 is reset by the input of the signal FS, a vertical blanking signal V is inputted to a CK terminal, thereby, 1 or 0 is Q outputted according to a first and second field periods. Thereby, at the time of interlace scanning a picture memory 1, a row address is designated from a first row, only odd number rows are sequentially designated in the first field, only even number rows are sequentially designated in the second field. At the time of non-interlace scanning the memory 1, the row address is designated from 0 the row and the address is designated sequentially for every row. Thereby, the picture information between the adjacent picture elements can be easily processed.

Inventors

  • 👤 Matsuhiko Takatani
  • 👤 高谷 松彦

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-07 16:36
CPC Classifications
—

Claims Analysis

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References Cited (Backward Citations)

JPS5119297A Cited
JPS54138331A Cited
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JPS6231286A Cited

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