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JPS63252464A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Mitsubishi Electric Corp
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Filing: 1987-04-09
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Granted: —
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Expires: 2007-04-09
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Abstract

Abstract PURPOSE:To inhibit even the potential fluctuation of a well, and to prevent the generation of a latch-up by forming a semiconductor layer having the same conductivity type as a substrate and an impurity in high concentration between the well having a conductivity type reverse to the substrate and the substrate. CONSTITUTION:A P-well 1 and an N-well 2 are shaped onto a P-type semiconductor substrate 12, and the substrate 12 is grounded through a P-type diffusion layer 5a and the P-well 1 through a P-type diffusion layer 5b. A source in a P channel MOSFET 4 is connected to a power supply VCC, a drain to a drain in an N channel MOSFET 3 and a source in the FET 3 to ground potential, thus constituting a CMOS inverter. A high-concentration P<+> layer 13 is formed between the substrate 12 and the N-well 2, thus narrowing the width of a depletion layer, then increasing junction capacitance.

Inventors

  • 👤 Narihito Yamagata
  • 👤 整人 山形

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 09:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854

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