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JPS63241965A Expired / Lapsed JP ⏱️ 0.0 years remaining

Insulated-gate field-effect transistor and manufacture thereof

Assignee: Toshiba Corp
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Filing: 1987-03-30
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Granted: —
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Expires: 2007-03-30
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Abstract

Abstract PURPOSE:To prevent source, drain junction breakdown strength from decreasing and a leakage from increasing while a punch-through or a short channel effect is suppressed by selectively forming a channel impurity layer at the center of a channel region. CONSTITUTION:A channel impurity layer 6 is selectively formed at a center except the ends of source, 4, drain 5 side ends of a channel region. Thus, even when a channel impurity layer 6 is formed in a relatively high concentration, it can suppress the increase in the junction leakage of the source, 4 the drain 5 and the decrease in its bonding breakdown strength. Since a channel surface electric field near the drain is reduced, an impact ionization can be suppressed. Since its threshold value is determined by the channel impurity layer at the center of the channel region, a short channel effect can be suppressed. As a result that the increase in the junction capacity of the source, the drain can be suppressed, high speed operation characteristic is obtained.

Inventors

  • 👤 Hiroshi Takatou
  • 👤 高東 宏

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 16:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/0217; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307

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