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JPS63201986A Expired / Lapsed JP ⏱️ 0.0 years remaining

2 port memory

Assignee: Panasonic Holdings Corp
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Filing: 1987-02-18
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Granted: —
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Expires: 2007-02-18
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Abstract

Abstract PURPOSE:To form a two port memory of a large capacity as a chip by designing the titled memory in a way that two independent addresses are accessed at readout and either of the two independent addresses at write only is to be accessed. CONSTITUTION:When a 1st word line W1 is selected at readout, the stored data Q is transferred to a 1st bit line B1. In selecting a 2nd word line W2, the stored data Q* is transferred to a 2nd bit line B2. Even in selecting the 1st word line W1 or the 2nd word line W2 at write, since two bit lines at write are used simultaneously, the write of the word line selected precedingly is finished, then the write of the word line selected next is to be executed. That is, even when the write is executed and the other write is to be executed, it is disregarded. Thus, a two port memory with a large capacity is mounted as a chip easily.

Inventors

  • 👤 Seiji Yamaguchi
  • 👤 山口 聖司

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 01:22
CPC Classifications
—

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS54107228A Cited
JPS60111394A Cited

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