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JPS63185040A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Mitsubishi Electric Corp
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Filing: 1987-01-27
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Granted: —
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Expires: 2007-01-27
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Abstract

Abstract PURPOSE:To suppress the intrusion of impurities into a transistor channel region and to obtain an excellent element isolating characteristic, by embedding semiconductor layers having the same conductivity type as that of a semiconductor substrate in grooves, which are formed in the surface of a silicon semiconductor substrate, and electrically isolating elements. CONSTITUTION:P-type polycrystalline silicon films 8 are embedded in grooves 8 formed in the surface of a p<-> type semiconductor substrate. Thus elements are isolated. Not only the same element isolating characteristic as that of a conventional semiconductor device is obtained, but also intrusion of p<->type impurities into the channel region of a transistor can be eliminated. Therefore, the width of the gate of the transistor becomes the length determined by the element isolating region. Increase in threshold voltage value can be prevented even in the transistor, in which especially short gate width is required. Since polycrystalline silicon is embedded in the silicon grooves 2, an impurity forming step can be omitted, and the manufacturing process can be shortened. The p<->type polycrystalline silicon film 8 is formed on only the side wall part and the bottom wall part of each silicon groove 32. An insulating film 3 is embedded in the remaining part of each silicon groove 2, and thus the surface of the silicon semiconductor substrate can be flattened.

Inventors

  • 👤 Masahiro Yoneda
  • 👤 昌弘 米田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 04:50
CPC Classifications
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