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JPS63185035A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Oki Electric Industry Co Ltd
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Filing: 1987-01-28
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Granted: —
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Expires: 2007-01-28
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Abstract

Abstract PURPOSE:To omit a wafer processing step and to improve the yield rate of a plating step, by forming bumps on at least one surface of a heat resisting wiring sheet, and connecting and conducting the lead-out electrodes of a semiconductor element and a tape carrier and also the tips of the inner leads, outer leads and the outer lead-out electrodes of the semiconductor element through the bumps. CONSTITUTION:A conduction path 21 comprising a copper foil is formed at the bottom part of a through hole at the opposite side of a polyimide tape 1 with respect to a semiconductor element 5. A current is conducted through the conduction path 21. Then bumps 22 are grown in through holes corresponding to lead-out electrodes and inner ends 20 by an electric plating method. The bumps 22 are positioned to the inner ends 20 of lead frames 11 and to the lead-out electrodes of the semiconductor element 5. The bumps are pushed with a bonding tool, and the bumps 22 are heated with a pulse current. Thus the metals of the bumps 22 are heated and compressed to the inner ends of the lead frames 11 and the lead-out electrodes of the semiconductor element 5. The inner ends 20 of the lead frames 11 are electrically connected and conducted to the conduction path 21 of the polyimide 1 tape 1 through the bumps 22. The conduction path 21 is electrically connected and conducted to the lead-out electrode of the semiconductor element 5 through the bumps 22.

Inventors

  • 👤 Yutaka Okuaki
  • 👤 奥秋 裕

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 19:53
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/701

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