amplifier circuit

Abstract

Abstract PURPOSE:To minimize the bottom area and the circumferential length of a source/drain region and reduce the junction capacitance of the source/drain region and facilitate the high speed operation of an amplifying circuit as a whole by surrounding the source/drain region, which is not connected to the source terminal of a MOS-FET which is connected to the source terminal with a gate electrode. CONSTITUTION:Reference numerals 2, 4 and 5 denote a gate electrode, a P-type active region connected to a source terminal and a P-type source/drain region surrounded by the gate electrode 2 respectively. The junction capacitance CAO of the source/drain region 5 is expressed by the following formula: CAO=W01.W 02.CBO+2(W01+W02).CSO, wherein CBO denotes the capacitance of the unit area of the bottom area and CSO denotes the capacitance of the unit length of the side surface and 2.(W01+W02) means a channel length. It is to be noted that, as the active region 4 is connected to the source terminal or the like, the influence of the junction capacitance is not taken into account. By changing the shape of the source/drain region of a MOS-FET, the junction capacitance and the bulk resistance, which have influence upon the operation speed of a circuit, of the source/drain region of the MOS-FET can be suppressed.

Inventors

• 👤 Hiroshi Koga
• 👤 広志 古賀
• 👤 Junichi Ukai
• 👤 鵜飼　純一

Bibliographic Details