Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To contrive to shorten the lengths of wirings for shift and shift clock signal wirings by a method wherein the wirings for shift and the shift clock signal wirings are respectively previously ready-designed in a storage logical cell as master patterns. CONSTITUTION:Master-slave type FFs 4a-4m are arranged in cell arrays 2b-2f. The FFs 4a-4m are arranged being aligned laterally in the direction of a cell array 2a and the cell arrays 2b-2f for constituting shift registers. In case an automatic arrangement and an automatic wiring are performed utilizing a CAD, a wiring 5b for shift for connecting the shift registers constituted of the FFs 4a-4c and the shift registers 4d-4f being arranged in the array 2c needs a lateral track. Provided that, when a difference between the values of (x) coordinates, on which cells are positioned, is small, the length to occupy in the lateral track of a wiring 5e for shift becomes shorter, while shift clock signal wirings 8b and 9b are each connected between the shift registers 4a-4c and 4d-4b using a vertical track only. In such a way, the lengths of the wirings become particularly shorter.

Inventors

• 👤 Hiroaki Nishi
• 👤 西　宏晃

Bibliographic Details