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JPS63152136A Expired / Lapsed JP ⏱️ 0.0 years remaining

Mounting process of semiconductor chip

Assignee: Fuji Electric Co Ltd
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Filing: 1986-12-17
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Granted: —
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Expires: 2006-12-17
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Abstract

Abstract PURPOSE:To mount a semiconductor chip without collapsing by a method wherein bumps are formed of high melting point solder while subsolders on a semiconductor part are made of low melting point solder to make the subsolders reflow into the high melting point solder at the temperature not exceeding the melting point. CONSTITUTION:Bumps 5 are formed of high melting point solder, e.g., within the range of 270-312 deg.C on a part of Al wiring of a semiconductor chip 1 through the intermediary of a primary metallic film. On the other hand, a eutectic solder 8 in melting point of 183 deg.C is sub-soldered on a thick conductor part 7 formed on the surface of a ceramic substrate 6. Next, when the face down bumps 5 of chip 1 are overlapped on the subsolders 8 of semiconductor part to be aligned in contact with one another heated at around 200-230 deg.C for flip chip bonding, the subsolders 8 are melted to be fusion-welded into the bumps 5 but the bumps 5 are not to be melted thus hardly collapsing the chip 1. Through these procedures, the distance between the surface of chip 1 and the surface of substrate 6 can be controlled.

Inventors

  • 👤 Yoshikiyo Usui
  • 👤 吉清 臼井

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 15:00
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/20; H10W72/251

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5773947A Cited

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