Multi-processor system

Abstract

Abstract PURPOSE:To omit the need to decide the priority of interruptions by arbitrating a common bus line when a slave processor board gives an interruption request to a master processor board. CONSTITUTION:When occurrence of interruptions are informed to the slave processor boards 2 and 3 from the interruption request generating circuits 6 and 8, the boards 2 and 3 perform the arbitrating jobs via a bus arbitrating circuits 12 and 13 to acquire a data bus 11. The processor board that acquired the bus 1 by arbitration delivers an interruption request signal through a gate circuit 14 or 16 to inform the occurrence of interruptions to a master processor board 1. At the same time, the interruption information given from an interruption information generating circuit 7 or 9 is written into an FIFO memory 5 via a gate circuit 15 or 17. Then the board 1 reads the interruption information out of the memory 5 and calls an interruption procedure in response to said interruption information to carry it out. Thus it is not required to decide the priority of interruptions.

Inventors

• 👤 Hisayoshi Totsuka
• 👤 戸塚　久義
• 👤 Akira Haruno
• 👤 春野　公

Bibliographic Details