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JPS63126338A Expired / Lapsed JP ⏱️ 0.0 years remaining

Data transmission-reception circuit

Assignee: NEC Corp
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Filing: 1986-11-17
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Granted: —
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Expires: 2006-11-17
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Abstract

Abstract PURPOSE:To contrive the simplification of a circuit constitution by using an address selection circuit so as to give the address of a transmission data and the address of a reception data switchingly to a memory and using one memory in common for transmission and reception. CONSTITUTION:A reception mode signal 206 is outputted from a timing signal generating circuit 1 in response to a reception mode command, a memory 2 is in the write state, a reception counter 5 counts the clock to output a reception address signal. The address is selected by the address selection circuit 7 receiving the transmission address from a transmission address counter 6 in response to the switching signal from the circuit 1 and given to the memory 2. Then the parallel reception data via a serial/parallel conversion circuit 4 is written in the memory 2. The parallel data is read from the memory 2 and the serial data is sent similarly via the parallel/serial conversion circuit 3, one memory is used in common for both the transmission and reception to attain cost-down.

Inventors

  • 👤 Hideaki Tokuchi
  • 👤 徳地 秀昭

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 02:13
CPC Classifications
—

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