Control method for clock signal supply in data processor

Abstract

Abstract PURPOSE:To reduce power consumption by providing a clock inhibiting instruction and inhibiting supply of a clock signal of a logic circuit if this instruction is read out. CONSTITUTION:When a micro instruction for clock supply request is read out, a signal 3d is set to the high level. This state is stored in a flip flop 300 by a clock 3b, and a signal 3e obtained by this operation is synchronized with a flip flop 301 by a clock 3a. A signal 3f synchronized with the clock 3a sets a flip flop 302 by the clock 3b to indicate the clock stop. A clock stop signal 3g is synchronized with the clock 3a by a flip flop 303, and clock gates 304-306 are controlled by a pair of signals 3h and 3i (the inverse of 3h), and a clock 3x corresponding to the clock 3a is stopped in the high-level state by a gate 305, and clocks 3y and 3z corresponding to clocks 3b and 3c are stopped in the low-level state.

Inventors

• 👤 Hideo Maejima
• 👤 前島　英雄
• 👤 Akihiro Katsura
• 👤 晃洋 桂
• 👤 Toshimasa Kihara
• 👤 利昌 木原
• 👤 Yasushi Akao
• 👤 赤尾　泰

Bibliographic Details