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JPS629677A Expired / Lapsed JP ⏱️ 0.0 years remaining

Field effect semiconductor device

Assignee: NEC Corp
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Filing: 1985-07-05
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Granted: —
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Expires: 2005-07-05
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Abstract

Abstract PURPOSE:To improve the vertical property of the side plane of a gate electrode and to obtain the FET without variability in the characteristics by using the gate electrode structure in which silicide of high-melting-point metal and a high-melting-point metal are laminated at least to three layers. CONSTITUTION:On a semi-insulating GaAs substrate 4, Si ions are implanted to form a GaAs active layer 3 and WSi 1 is deposited by sputtering. Subsequently, W 2 of 100nm, successively WSi of 100nm and W 100nm are deposited in order, thereby forming the gate electrode film of four-layer structure in which W 1 and WSi 2 are laminated alternately to the whole thickness 400nm. Next, a resist is formed in the part which will serve as a gate electrode and the four-layer structure gate electrode film in the region uncovered with the resist is removed by dry etching using SF6. The side shape of the gate electrode at that time has the more improved vertical property compared with the side plane of a conventional electrode of double-layer structure.

Inventors

  • 👤 Mikio Kanamori
  • 👤 金森 幹夫

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 13:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D64/00; H10D64/60; H10D64/64; H10D62/00; H10D62/80; H10D62/85

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