Semiconductor integrated circuit

Abstract

Abstract PURPOSE:To improve the operating speed of a whole master slice type semiconductor integrated circuit without augmenting the area of the chip by a method wherein the MOS Trs of parts in the circuit are each provided with contacts for reducing a parasitic resistance plural pieces. CONSTITUTION:A source region 12 and a drain region 13 are each provided with contacts 221 and 222 and contacts 231 and 232 two pieces by two pieces and the respective fellow contacts are connected with first layer wirings 15, tunnel wirings 16 which are layers different from the wirings 15 and through holes 321 and 322, or 331 and 332. At this time, the resistance components of the wirings 15 and 16 are sufficiently smaller compared to those of the wirings 15 and 16 are sufficiently smaller compared to those of the source and drain regions and can be ignored. By this way, in case the overall resistivity between lead-out wirings S-D from each one contact of the source and drain regions is calculated, the resistance component between the S-D becomes smaller. A parasitic resistance component can be reduced in order further increasing the number of contact and by connecting those fellow contacts with wirings.

Inventors

• 👤 Yukio Ozawa
• 👤 幸雄 小澤

Bibliographic Details