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JPS626494A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor storage device

Assignee: NEC Corp
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Filing: 1986-03-18
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Granted: —
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Expires: 2006-03-18
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Abstract

Abstract PURPOSE:To obtain a memory capable of executing high-speed electric discharging by discharging residual electric charge at the time of writing which is left on a connection line at the time of verify operation after writing information on a memory cell by a discharging means. CONSTITUTION:After the completion of writing on a cell, a signal D is activated to turn on a discharging transistor (TR) Q3. Consequently, charge on a digit line 1 and charge on a sense amplifier connection line 5 are rapidly and precisely discharged to a reference electric potential through the TR Q3. After the completion of discharging, the signal D is inactivated to transfer the current operation mode to a verify mode. In said mode, a cell Q1 is kept at a selecting state by signals X1, Y1 and is in a reading mode, information written on the cell is transferred to a sense amplifier 6 through a TR Q2, amplified and extracted from an output terminal 7. The extracted information coincides with the information written on the cell without the influence of residual charge and precise verify operation can be attained.

Inventors

  • 👤 Takahiko Urai
  • 👤 浦井 孝彦

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 10:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3427; G11C16/10; G11C16/12; G11C16/22; G11C16/225

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS56137591A Cited
JPS60263399A Cited

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