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JPS6258487A Expired / Lapsed JP ⏱️ 0.0 years remaining

Static type memory

Assignee: Toshiba Corp
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Filing: 1985-09-06
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Granted: —
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Expires: 2005-09-06
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Abstract

Abstract PURPOSE:To reduce the power consumption due to the decrease in the electric current consumption time by executing a precharging equalizing action by a precharging equalizing circuit until the selection of a section word line is started in a selecting cycle, concerning the bit line in the selecting section. CONSTITUTION:At respective columns in the selecting section, before the selection of a section word line SWL is selected in an address cycle, a bit line precharging equalizing circuit 1 is operated by a bit line precharging signal phiPC, and bit lines BL and the inverse of BL are precharged and equalized. Next, after a section word line SWL is selected and a memory cell is selected, the bit line precharging and equalizing circuit 1 comes to be the off condition, at the time of the reading mode, the bit lines BL and the inverse of BL are driven only by the selected memory cell and therefore, the bit line at the low electric potential side drops from the precharging level to a VSS level finally.

Inventors

  • 👤 Takayuki Otani
  • 👤 大谷 孝之

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 23:36
CPC Classifications
—

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS6061986A Cited
JPS60119693A Cited

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