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JPS6249644A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1985-08-29
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Granted: —
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Expires: 2005-08-29
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Abstract

Abstract PURPOSE:To prevent the formation of a texture to increase the etching rate and of an abnormal part of composition in a PSG layer formed on the step difference part, by implanting phosphorus ions in the insulating layer and redistributing the implanted phosphorus in an insulating layer by thermal treatment. CONSTITUTION:An insulating layer 104 constituted of silicon dioxide as a main component is stuck so as to cover a wiring pattern 3 formed on the semiconductor substrate 1. The phosphorus ions are implanted in this insulating layer 104, and the implanted phosphorus is redistributed in the insulating layer 104 by thermal treatment. In order to form a second PSG layer 14 which has nearly uniform P density for its whole part, the implanted phosphorus is redistributed by the annealing in nitrogen atmosphere. A contact window 7 to expose the lower Al wiring layer 3 in a second PSG layer 14 is formed by the formation of the side surface 7 of the contact window 7 so as to incline by a reflow process. Then an aluminum layer is formed, which is subjected to patterning to form the Al wiring layer 9.

Inventors

  • 👤 Masao Sugita
  • 👤 杉田 正夫
  • 👤 Yoshio Uchida
  • 👤 内田 佳夫
  • 👤 Kenji Koyama
  • 👤 小山 堅二
  • 👤 Atsuhiro Tsukune
  • 👤 敦弘 筑根
  • 👤 Masahide Nishimura
  • 👤 西村 正秀

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 14:32
CPC Classifications
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