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JPS6238615A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor circuit

Assignee: Fujitsu Ltd
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Filing: 1985-08-14
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Granted: —
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Expires: 2005-08-14
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Abstract

Abstract PURPOSE:To quicken the leading and to avoid much deterioration of the degree of circuit integration by combining an N-N type output buffer and a P-N type output buffer and using transistors (TR) at the pull-down side in common use for the both. CONSTITUTION:A P-channel MOS TR Q1 and an N-channel MOS TR Q2 constitute the P-N type output buffer and CMOS inverters Q3, Q4 and N-channel MOS TRs Q5, Q2 constitute the N-N type output buffer and the TR Q2 is used in common for the both. The N-channel MOS TR Q5 having a large driving capability at the leading drives an output terminal load circuit and the beta of the TR Q5 decreases as the level of an output terminal OUT is increased to decrease the drive capability, the P-channel MOS TR Q1 drives the load circuit at this point of time to boost the level of the output terminal OUT up to a voltage Vcc.

Inventors

  • 👤 Kazuhiro Adachi
  • 👤 和広 安達

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 11:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721

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