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JPS62284518A Expired / Lapsed JP ⏱️ 0.0 years remaining

Integrated circuit

Assignee: Fujitsu Ltd
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Filing: 1986-06-02
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Granted: —
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Expires: 2006-06-02
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Abstract

Abstract PURPOSE:To obtain a desired delay time by providing a delay circuit constituted by connecting plural logic elements in series and a control circuit which selects outputs of the respective logic elements. CONSTITUTION:This integrated circuit incorporates the delay circuit 1 constituted by connecting plural logic elements 11-1n in series, a counter 2 which counts input pulses supplied to the delay circuit 1, and the selecting circuit 3 which selects the output pulses of the logic elements 11-1n. A figure shows that the time Td from the trailing edge to the leading edge of the output (o) of a monostable multivibrator when the monostable multivibrator is connected between the selecting circuit 3 and delay circuit 1 is equal to the sum of delay times of the logic elements 11-1m. This time Td is found from the counted value of the counter 2 within a specific time, so the logic elements 11-1m are so selected that the time has a desired value. Consequently, the desired delay time Td is obtained.

Inventors

  • 👤 Toshiyuki Muta
  • 👤 俊之 牟田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 23:07
CPC Classifications
—

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