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JPS62276643A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory control method

Assignee: Fujitsu Ltd
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Filing: 1986-05-26
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Granted: —
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Expires: 2006-05-26
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Abstract

Abstract PURPOSE:To use memory devices having different speeds and capacity in accordance with processing purposes and to improve the whole processing speed by discriminating a sort signal from each memory device by a central control device and using a control circuit corresponding to the sort of the memory. CONSTITUTION:A comparing/selecting circuit 17 in the central control device 1 receiving a sort a signal CL indicating the sort of a memory, e.g., a DRAM, an SRAM, form either one of memory devices 20, 30 through either one of sort signal lines 120, 121 selects either one of the memory devices 20, 30 and either one of control devices 14, 18 based on an address in an address register 11 and the sort signal CL and sends a selecting signal SEL to either one of selection lines 110, 111 to specify either one of the memory devices 20, 30 and either one of the control circuits 14, 18 corresponding to the sort of the specified memory device through either one of specification lines 50, 51. The specified control circuits 14, 18 writes data in the specified memory devices 20, 30.

Inventors

  • 👤 Hiroko Horii
  • 👤 堀井 弘子
  • 👤 Etsuji Kuraya
  • 👤 倉矢 悦治

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 16:01
CPC Classifications
—

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References Cited (Backward Citations)

JPS5219925A Cited

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