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JPS62260418A Expired / Lapsed JP ⏱️ 0.0 years remaining

Flip-flop circuit

Assignee: NEC Corp
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Filing: 1986-05-06
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Granted: —
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Expires: 2006-05-06
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Abstract

Abstract PURPOSE:To attain high-speed processing without using a highspeed clock by outputting a data output of a latch circuit in latch operation to a data output terminal by a switch circuit. CONSTITUTION:When data changes from DATA1 into DATA2 during the clock T2, the level at a data output terminal Q1 of the latch circuit 21 goes to the level of the DATA2. When the clock CK descends, the latch circuit 21 latches the DATA and the level of the data output terminal Q2 of a latch circuit 22 goes to the level of the DATA2 and the switch circuit is changed over to the position of the data output terminal Q1 of the latch circuit 21. Further, the data output terminal Q is connected to the data output terminal Q1 of the latch circuit 21 during a time T3 to keep the DATA 2. Through the repetition of the operation above, the circuit fetches the DATA at the leading/falling of the clock CK to output the data to the terminal Q.

Inventors

  • 👤 Hiroshi Takizawa
  • 👤 瀧澤 廣志

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 21:52
CPC Classifications
—

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS6062234A Cited
JPS60142732A Cited

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