Wafer scale integrated circuit

Abstract

Abstract PURPOSE:To reduce the area of a wafer used for testing each unit integrated circuit, and to improve the activity ratio of the wafer and the degree of integration thereof by mounting one pattern compressor to each of the unit integrated circuits and fitting one pseudo-random number generator in common with a plurality of the unit integrated circuits. CONSTITUTION:Aggregates such as three groups of ones 41, 42, 43 of unit integrated circuits having the same function are formed in a wafer 4. A plurality of the unit integrated circuits having the same function are each contained in respective aggregate 41, 42, 43. That is, a plurality of the unit integrated circuits 11 are included in the aggregate 41, a plurality of the unit integrated circuits 12 in the aggregate 42 and a plurality of the unit integrated circuits 13 in the aggregate 43 respectively. 21 of common pseudo-random number generators 21, 22, 23 is connected to each of the unit integrated circuits 11 constituting the aggregate 41, 22 is connected to each of the unit integrated circuits 12 organizing the aggregate 42, and 23 is connected to each of the unit integrated circuits 13 forming the aggregate 43. One pseudo-random number generator is mounted in common at every unit integrated circuit having the same function, thus improving the activity ratio of the wafer.

Inventors

• 👤 Koichi Yamashita
• 👤 公一 山下

Bibliographic Details