Patent JPS6218751A successfully refreshed from Google Patents.
← Back to Patent Explorer
JPS6218751A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: NEC Corp
•
Filing: 1985-07-17
•
Granted: —
•
Expires: 2005-07-17
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To largely reduce the area of a memory cell by forming a hole at a semiconductor substrate and using the bottom of the hole and a part of a wall as the capacity, and the wall except the capacity as the gate region. CONSTITUTION:A hole 12 is formed at a P-type Si substrate 10, a P<+> type channel stopper 11 is formed, a polysilicon 15 is buried through SiO2 films 13, 14 to the midway of the hole, and coated with an SiO2 film 16. Further, a polysilicon gate 18 is formed through a gate oxide film 17 on the hole wall, coated with an interlayer insulating film 23, a window is opened on a diffused layer 19, and aluminum electrodes 22 are attached. According to this configuration, the capacity of a dynamic memory cell and a transistor are formed in the hole, and when the hole is deepened, the cell capacity can be increased without increasing the area.

Inventors

  • 👤 Yukinobu Murao
  • 👤 幸信 村尾

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 14:35
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/39; H10B12/395

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag