Gate array lsi device

Abstract

Abstract PURPOSE:To enable the titled device of high performance to be easily obtained by shortening the wiring length by increasing the degree of freedom in wiring design with the third layer wirings. CONSTITUTION:The connection in each of logic blocks 1 and 2 is carried out by the first layer wiring, and the wiring in each of memory macros M1, M2...M8 is carried out by the first layer wiring and the second layer wiring. Wirings A, B, C, etc. connected directly to an I/O buffer 4 from each of the logic blocks 1 and 2 are carried out by the first layer wiring or the second layer wiring. The wriring H passing from the memory macro M3 through the memory macro M1 to the terminal around the memory block, wiring I passing from the memory macro M4 through the memory macro M2 to the periphery f the memory block Mb, and wiring J passing from the logic block 1 through the memory block 3 to the I/O buffer 4 are carried out by the third layer wiring. The use of the third layer wiring enables the free utilization of the region in the memory block 3 as the wiring channel and the connection of circuits with the shortest distances.

Inventors

• 👤 Tomoaki Tanabe
• 👤 田辺　智明
• 👤 Shigeru Fujii
• 👤 藤井　滋

Bibliographic Details