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JPS6197839A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1984-10-18
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Granted: —
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Expires: 2004-10-18
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Abstract

Abstract PURPOSE:To contrive to prevent the generation of cracks by keeping the moisture resistance of Si3N4 layers by a method wherein the first insulation layer is adhered by covering the wiring layer, and the step-wise difference part or recess of the first insulation layer is filled with spion glass; thereafter, the substrate is coated with an Si nitride layer or with the second insulation layer and an Si nitride layer in this order. CONSTITUTION:The patterned wiring layer is formed on a semiconductor sub strate 1, and the first insulation layer is adhered by covering the wiring layer. After the stepwise difference part or recess of the first insulation layer is filled with spion glass, the substrate is coated with an Si nitride layer or with the second insulation layer and an Si nitride layer in this order. Spion glass can fill the stepwise difference part or recess of the insulation layer adhered on the substrate by spin-coating and can be fixed as silicon dioxide (SiO2) by bak ing. Besides, interposing the insulation layer between the substrate or the wiring layer causes little possibility of damaging the reliability of the titled device. Coating this flattened insulation layer with an Si3N4 layer produces no stress to the latter layer and does not inhibit moisture resistance.

Inventors

  • 👤 Atsushi Nakano
  • 👤 淳 中野
  • 👤 Takashi Yabu
  • 👤 薮 敬司
  • 👤 Kazunari Shirai
  • 👤 白井 一成
  • 👤 Shinji Sugaya
  • 👤 慎二 菅谷
  • 👤 Koji Hashimoto
  • 👤 広司 橋本

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 10:04
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5472971A Cited
JPS58135645A Cited

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