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JPS6187322A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Seiko Epson Corp
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Filing: 1984-09-13
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Granted: —
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Expires: 2004-09-13
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Abstract

Abstract PURPOSE:To enable the formation of the shallow N type diffused junction layer of a low sheet resistance at low cost by forming an SOPSG on a surface of silicide followed by a heat treatment using a halogen lamp. CONSTITUTION:On a silicon substrate 1, a gate oxide film 8, a polycrystalline silicon gate electrode 10 and a side wall insulating film SiO2 9 are formed. After forming a high-melting point metal or a high-melting point metal layer 11 on the gate electrode and the source and drain selectively, the substrate is coated with an SOPSG12 by a spin coater and the coated substrate is baked and is subjected to a high-temp. and short-time heat treatment by use of a halogen lamp to form a MOS.FET having a shallow N type diffusion layer 13. In this case, the shallow junction reduces a junction capacity and makes switching of the MOS.FET faster and at the same time, it enables miniaturization of the MOS.FET.

Inventors

  • 👤 Juri Kato
  • 👤 樹理 加藤

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 14:38
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171

Claims Analysis

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References Cited (Backward Citations)

JPS55110036A Cited
JPS58168221A Cited
JPS58223320A Cited
JPS59105366A Cited

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