Semiconductor memory device

Abstract

Abstract PURPOSE:To prevent to receive influences of capacity coupling with other bit lines and to make an integrated circuit suitable when a sense operation is executed by using a pair of bit lines which shares a sense amplifier and making bit lines and a plate electrode of the memory cell in common. CONSTITUTION:A memory cell which is composed of one MOSTR and one capacitor is integrated in a matrix manner on the semiconductor substrate. A memory cell group 2 is continued serially between bit line inversions BLI and BLI which share a sense amplifier 1. The j-th memory cell of the cell group 2 is connected to the inversion BLI at a drain of TRQ24, a source is connected through a capacitor C24 to BLI, and the gate is connected to the j-th word line WLI. The i-th memory cell is connected to BLI at the drain of TRQ23. By such a composition, the influence of capacity coupling with other bit lines is prevented to be received and can be integrated highly.

Inventors

• 👤 Yasushi Sakui
• 👤 康司 作井

Bibliographic Details