Manufacture of fet

Abstract

Abstract PURPOSE:To obtain narrow width having extremely high accuracy, and to shorten gate width remarkably by applying a first insulating layer onto the surface of a semiconductor substrate with an active region, boring an opening section through photolithography and forming a second insulating layer called a side wall on the inside of the opening section. CONSTITUTION:An N-type active region 2 is diffused and shaped to the surface layer section of a semi-insulating GaAs substrate 1, the whole surface containing the region 2 is coated with an SiO2 first insulating film 3, and an opening 4 is bored between source and drain forming sections. An Si3N4 second insulating film 5 is applied while burying the opening 4, and the film 5 being in contact with the film 3 is left only on the side wall of the opening 4 through anisotropic etching and used as a side wall, thus bringing the width of the opening 4 to a narrow opening 6. A P-type region 7 is shaped to the surface layer section of the region 2 exposed into the opening 6 through a diffusion, and a gate electrode 10 is formed to the region 7. A mask composed of a resist film 9 is shaped onto the electrode 10, the film 3 on the region 2 is removed through etching, and P-type source-drain regions are formed to the removed film 3.

Inventors

• 👤 Yoji Kato
• 👤 加藤　洋二
• 👤 Seiichi Watanabe
• 👤 誠一 渡辺

Bibliographic Details