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JPS6167318A Expired / Lapsed JP ⏱️ 0.0 years remaining

Integrated circuit of matrix switch

Assignee: Fujitsu Ltd
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Filing: 1984-09-11
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Granted: —
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Expires: 2004-09-11
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Abstract

Abstract PURPOSE:To sharply reduce crosstalks at a high frequency in a matrix switch integrated circuit of (nXn) channels arrayed on an IC, by arraying matrix switches in (nXn/2)X2. CONSTITUTION:The matrix switch integrated circuit of this invention is composed of (nXn) pieces of switch cells (1-1, 1-2-1-n), (2-1, 2-2-2-n), (n-1, n-2-n-n) and (n) pieces of output buffers 3-1, 3-2-3-n. Since the matrix switch integrated circuit is formed in such a way, the wiring intersection is eliminated on the output side and remains on the input side only. As a result, crosstalks at a high frequency can be reduced sharply.

Inventors

  • 👤 Tomoyuki Otsuka
  • 👤 友行 大塚
  • 👤 Yoshiro Nakayama
  • 👤 中山 吉郎
  • 👤 Haruo Shimizu
  • 👤 清水 治夫

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 07:53
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5935448A Cited
JPS59155145A Cited

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