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JPS6154656A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
•
Filing: 1984-08-24
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Granted: —
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Expires: 2004-08-24
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Abstract

Abstract PURPOSE:To enlarge the form of a chip in a package as a lower layer by shaping a pin to a soldering pad section for a package and forming a hole to a pad section for the lower-layer package. CONSTITUTION:Preparatory solder 18 is attached into a hole 14a in a lower- layer package 13, and a corresponding pin 12a in an upper-layer package 11 is inserted and conneced through a reflow. A glass material 21 is affixed to sections except holes 14 and hermetically sealed, and a chip 17 in the package 13 is sealed by the lower surface of the package 11. An interior-finish pattern 19 is connected to each hole 14 through preparatory solder 18, and connected to several element in the chip through leads 20. A chip 17 having the same shape as the chip 17 is housed in the package 11, and sealed by a cover 15. According to said constitution, the size of the chips in the packages as upper and lower layers can be made the same, and a cap exclusive for the lower-layer package can be omitted.

Inventors

  • 👤 Teruyuki Nabeta
  • 👤 鍋田 照行
  • 👤 Tetsushi Wakabayashi
  • 👤 哲史 若林

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 03:59
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/421; H10W70/424; H10W90/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/50; H10W90/701; H10W90/721; H10W90/722; H10W90/751; H10W90/754

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5066168A Cited
JPS5688341A Cited

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