Patent JPS6142159A successfully refreshed from Google Patents.
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JPS6142159A Expired / Lapsed JP ⏱️ 0.0 years remaining

Package of electronic circuit

Assignee: NEC Corp
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Filing: 1984-08-02
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Granted: —
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Expires: 2004-08-02
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Abstract

Abstract PURPOSE:To obtain the package substrate of an electronic circit of low cost and high density by a method wherein a high-temperature calcined substrate is joined to a low-temperature calcined substrate at the part which needs micro fabrication and density increase with a rubber conduction only in the thickness direction. CONSTITUTION:The high-temperature calcined substrate 11 has a power source circuit 11 in its internal layer and through holes 14 that connect pin pads 12, connection pads 13, and the internal layer. The pin pad 12 is brazed to the connection pin 3. The connection pad 13 is connected to the connection pad 21 for the low-temperature calcined substrate 2 via anisotropic rubber sheet 4. Next, this substrate 2 is produced by low temperature calcination of a green sheet, and the connection pad 21 and a via hole 22 are made of Au or the like. A micro pattern 23 and an insulation layer 24 of thick film paste are made in multilayers on the substrate 2. An IC connection pad 25 is made of Au plating. The substrate 1 is connected to the substrate 2 by sandwiching the anisotropic rubber sheet 4.

Inventors

  • 👤 Takeshi Kiyono
  • 👤 健 清野
  • 👤 Hikari Kimura
  • 👤 光 木村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 22:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W90/401; H05; H05K; H05K1/00; H05K1/02; H05K1/03; H05K1/0306; H05K1/14; H05K1/144; H10W90/701; H10W90/751; H10W90/754

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