Semiconductor memory

Abstract

Abstract PURPOSE:To shorten test time by executing a action which is serially performed conventionally, in parallel at the unit of plural cell blocks. CONSTITUTION:At the time of testing, ''0'' is given to a mode change-over terminal 1, and four cell blocks in a memory cell array 8 are simultaneously selected regardless of an address signal which is given to address signal terminals A12 and A13. Since an address in the column direction is designated based upon the result that the address signal which is given to address signal terminals A7- A11 is decoded by a column decoder 4, writing and reading can be simultaneously executed one by one for respective cell blocks, in total four memory cells. One out of four data is outputted to a data output terminal Dout. A checking circuit A checks 4 data, and when all are the same, ''1'' is outputted and except the data ''0'' is outputted to an error signal output terminal 2.

Inventors

• 👤 Takemi Igarashi
• 👤 五十嵐　丈美

Bibliographic Details