Master slice ic device

Abstract

Abstract PURPOSE:To enable gate-contact to wire strightly by a method wherein FET gate-contact region, where is located facing to an adjoined FET row opposedly, is arranged in directon of an element disposition within an FET row. CONSTITUTION:A gate-contact region 1a is arranged in parallel direction to FET row direction of a faced FET element region 1a, and is provided the length of two wiring channels. As the result, X, Y input wiring 8 and 9 can be formed respectively in space of one chennel, and a gate input wiring is housed on the gate-contact region 1a, then objective circuit function enable to realize fewer wiring channel than conventional method. Thus, more complicated logic circuit can be formed on the same scale master slice substrate conventional.

Inventors

• 👤 Gensuke Goto
• 👤 後藤　源助

Bibliographic Details