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JPS6134793A Expired / Lapsed JP ⏱️ 0.0 years remaining

Diagnosing and error correcting device in dynamic memory device

Assignee: Hitachi Ltd
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Filing: 1984-07-27
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Granted: —
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Expires: 2004-07-27
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Abstract

Abstract PURPOSE:To improve reliability without reducing performance of a memory device by re-writing diagnosis and corrected data with a scheduled refreshing cycle. CONSTITUTION:When hard errors occur at a package with a memory array 1, the package is changed over to one package of a preliminary memory array 21. An action control circuit 26 receives a CNT33 and an REF31, decodes respective action modes of read/write and read refreshment and sends them to the memory array 1 and the preliminary memory array 21. Here, MRSELs 0-9 and MCSELs 0-9 are respectively selection signals to selectively supply RASs 0-3 and CASs 0-3 to one of memory packages 0-9, and by energizing MRSELs 8 and 9 instead of one pair out of MRSELs 0-7 and MCSELs 0-7, the memory package can be changed over from the memory array 1 to the preliminary array 21.

Inventors

  • 👤 Yasuhiko Matsuura
  • 👤 松浦 泰彦

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-26 23:32
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/106; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C8/00; G11C8/18; G06F11/22; G06F11/2205; G11C29/00; G11C29/70; G11C29/76

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