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JPS6132478A Expired / Lapsed JP ⏱️ 0.0 years remaining

Nonvolatile memory

Assignee: Seiko Instruments Inc
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Filing: 1984-07-24
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Granted: —
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Expires: 2004-07-24
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Abstract

Abstract PURPOSE:To construct the titled device in such a manner that charge outflow from a floating gate electrode hardly occur even when voltage is impressed on the drain region, by a method wherein the neighborhood of the surface of a readout region surperposing on the floating gate electrode via insulation film is formed of a low-concentration impurity region of the second conductively type. CONSTITUTION:A source region 2 and a drain region 3 are both formed of an N type impurity region of high concentration, but an N type impurity region 35 of low concentration is formed in the drain region 3 at the part under the floating gate electrode 5. Except for this region 35, this device is the same as a nonvolatile memory of normal channel type. Since this nonvolatile memory is provided with the low-concentration impurity region 35 in the drain region 3 at the part under the floating gate electrode 5, the voltage between the drain region 3 and the floating gate electrode 5 in a state that this electrode 5 is electrified negatively, and that a positive voltage is impressed on the drain region 3 is absorbed to a depletion layer in the surface part of the region 35; accordingly, the voltage impressed directly on the insulation film 7 is alleviated.

Inventors

  • 👤 Yutaka Hayashi
  • 👤 豊 林
  • 👤 Masaaki Kamiya
  • 👤 昌明 神谷
  • 👤 Yoshikazu Kojima
  • 👤 芳和 小島

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 21:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS56104473A Cited

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