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JPS61287254A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Ltd
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Filing: 1985-06-14
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Granted: —
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Expires: 2005-06-14
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Abstract

Abstract PURPOSE:To improve the connecting strength and the reliability by providing a plurality of connecting points of internal wirings with a lead terminal in a package substrate. CONSTITUTION:A package substrate 1 is composed of a multilayer wiring ceramic substrate, a semiconductor chip 3 is contained in a cavity 2, and connected by wirings 5 with a terminal 4. Internal wirings 8, 11 are formed of W-metallized layer, and the internal wirings 9 are formed of through hole wirings of W-metallized layer. The end of the wirings 9 is connected with the W-metallized layer 10 on the bottom of the substrate 1 to connect the wirings 11 with the W-metallized layer 12 of the side of the substrate 1, a lead terminal 7 is bonded through Ni-plating film 13 and an Au-plating film 14, an Ni-plating film 15 and an Au-plating film 16 are again superposed, and coated to complete it.

Inventors

  • 👤 Hisashi Komabayashi
  • 👤 駒林 久士
  • 👤 Toshiaki Ono
  • 👤 俊昭 小野
  • 👤 Toru Ishida
  • 👤 徹 石田
  • 👤 Tamotsu Arai
  • 👤 荒井 保

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 09:04
CPC Classifications
H; H10; H10W; H10W90/00; H10W90/701; H10W72/00; H10W72/50; H10W72/541; H10W72/5449

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