Parallel data transmitter

Abstract

Abstract PURPOSE:To omit the transmission of a synchronizing timing signal by changing the logic of at least one bit out of bits obtained by combining a data signal with a parity signal at each data on the transmitter side, and detecting the logic changing point of the bit on the receiver side, and generating a synchronizing timing signal. CONSTITUTION:The output of a parity forming circuit 2 is inputted to a latch circuit 4, and only when both bit patterns completely coincide with each other and logic ''0''s are outputted from all exclusive OR gates 15,...16, a logic ''0'' signal is outputted from an OR gate 17 to control a selecting circuit 19 and the output of an inverter 18 is inputted to a latch circuit 4. Therefore, at least 1 bit out of the output of the latch circuit 4 is changed at its logic at each data. Since at least 1 bit out of the output bits of a receiving circuit 11 is changed at its logic at a data changing point, at least one of monostable multivibrators 25,...27 is triggered to reproduce a synchronizing timing signal and control the writing of said timing signal in a latch circuit 12 through an OR gate 28 and a delay circuit 29.

Inventors

• 👤 Yoji Komatsu
• 👤 陽二 小松

Bibliographic Details