Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To improve the integration by wiring the first layer metal in a lateral direction, the second layer metal in a longitudinal direction, and providing a connecting hole for connecting the first layer with the second layer, thereby wiring the passing wirings in a cell, alleviating the complication in a wiring region, and reducing the area of the wiring region. CONSTITUTION:Three passing wirings are provided in standard cells 4 of NAND, NOR, F/F and 4-bit ADDER, and the three second layer metals 6, 6, 6 are wired in parallel. The three first layer metal patterns 5, 5, 5 are formed perpendicularly thereto, thereby enabling to use in combination any two passing wirings. For example, in Fig. b, a and c' or a' and c are connected by a through hole 7 therebetween.

Inventors

• 👤 Tamotsu Hiwatari
• 👤 樋渡　有

Bibliographic Details