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JPS61202467A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: NEC Corp
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Filing: 1985-03-05
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Granted: —
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Expires: 2005-03-05
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Abstract

Abstract PURPOSE:To reduce hot carrier implanting phenomenon at a high speed by forming a silicide layer in a boundary over a polycrystalline silicon layer, and providing a high melting point metal extended on an insulating film on a drain diffused layer to reduce the resistance of a gate electrode. CONSTITUTION:A gate insulating film 103 is provided on an active region of a transistor surrounded by a field insulating film 102 on the surface of a semiconductor substrate 101, and a polycrystalline silicon 104 implanted with an impurity is formed at the prescribed position of the film 103. The upper layer of the silicon 104 is coated with a high melting metal 105 to be silicified with a boundary to be coupled to form integrally a gate electrode. An opposite conductive type low density source diffused layer 106 to the substrate 101 and a low density drain diffused layer 107 are formed in the substrate 101 of the lower layer side of the metal 105 contacted on the film 103, and a high density source diffuse layer 108 and a high density drain diffused layer 109 are formed under the film 103 not coated with metal 105.

Inventors

  • 👤 Minoru Araki
  • 👤 荒木 稔

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 06:55
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/671; H10D30/00; H10D30/60; H10D30/601; H10D30/605

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