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JPS6096906A Expired / Lapsed JP ⏱️ 0.0 years remaining

Gaas fet circuit

Assignee: NEC Corp
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Filing: 1983-10-31
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Granted: —
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Expires: 2003-10-31
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Abstract

Abstract PURPOSE:To obtain excellent high-frequency characteristics and balancing characteristics by connecting a source electrode of the 3rd FET to a common connecting point of source electrodes of two FETs and connecting its gate to a high-frequency signal input terminal. CONSTITUTION:An FET48 is provided to correct the loss of a high-frequency current flowed to the source of an FET47. The presence of the FET48 allows the input high-frequency signal fed to a terminal 6 to be fed to the gate of an FET46 and also to the gate of the FET48 to correct the high-frequency current flowed to a resistor 21. As a result, the high-frequency current flowed to the source and drain of the FET47 is increased and the level of output terminals 7 and 8 is arranged. Thus, an unbalance/balance exchange circuit with excellent high-frequency characteristics and well-balanced output levels is realized on a GaAs wafer by utilizing the high-speed property of a GaAs FET.

Inventors

  • 👤 Noboru Kusama
  • 👤 草間 昇

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 16:32
CPC Classifications
—

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