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Patent JPS6089979A successfully refreshed from Google Patents.
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JPS6089979A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1983-10-24
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Granted: —
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Expires: 2003-10-24
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Abstract

Abstract PURPOSE:To improve the uniformity of the threshold voltage and the reproducibility of an FET by alternately laminating two types of compound semiconductor layers at least one of which contains an element not common to both, and forming a gate electrode on the surface from which the semiconductor laminated structure is selectively removed. CONSTITUTION:A non-doped GaAs layer 12 and an N type Al0.3Ga0.7As layer 13 are grown in the prescribed thicknesses by, for example, a molecular beam epitaxial growing method on a GaAs substrate 11. Further, an N type GaAs layer 14 and an N type Al0.3Ga0.7As layer 15 which continuously contains Si at the prescribed rate are alternately laminated so that the thicknesses of the layers are set to the prescribed values. The layer 13 is an electron supply layer so that the impurity density and the thickness are selected to obtain the upper limit of the gate threshold voltage when the gate electrode is formed thereon. The impurity density, the thicknesses of the layers 14, 15, and the thickness of the layers are selected with respect to the range of the gate threshold voltage and the allowable irregular width.

Inventors

  • 👤 Takashi Mimura
  • 👤 高志 三村
  • 👤 Shigeru Kuroda
  • 👤 黒田 滋

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 23:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/161; H10D62/80; H10D62/81; H10D62/815; H10D62/8161; H10D62/8162; H10D62/8164

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