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JPS6080244A Expired / Lapsed JP ⏱️ 0.0 years remaining

Element isolation method of semiconductor device

Assignee: Hitachi Ltd
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Filing: 1983-10-07
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Granted: —
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Expires: 2003-10-07
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Abstract

Abstract PURPOSE:To reduce stress to a substrate and eliminate generation of crystal defect by vertically providing many pole-like projections consisting of substrate within a groove without filling the groove provided in the isolation region with an oxide at one time on the occasion of insulating and isolating a pluality of semiconductor elements formed on the semiconductor substrate but instead changing it to an oxide in expanded volume by the heat processing and filling the groove with the oxide. CONSTITUTION:On the occasion of providing element isolation regions between the active regions 208 formed on the semiconductor substrate 204, the SiO2 film 205 and Si3N4 film 206 are stacked and deposited on the entire part of substrate. Next, the active region 208 is covered with a resist film 207 and a groove 213 for element isolation is formed by the etching. In this case, the groove 213 is not provided entirely and many pole-like projections 210 consisting of substrate 204 having the films 206 and 205 at the surface vertically remain herein. Thereafter, the projections 210 is changed to oxide in expanded volume by the heat processing and simultaneously the oxide directly connected thereto is generated at the bottom surface. After this area is buried with the oxide 212, the films 206 and 205 are removed.

Inventors

  • 👤 Yoshifumi Kawamoto
  • 👤 川本 桂史
  • 👤 Tokuo Kure
  • 👤 久礼 得男
  • 👤 Masayuki Nakada
  • 👤 昌之 中田
  • 👤 Shinji Okazaki
  • 👤 信次 岡崎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 09:02
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17

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