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JPS607690A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory

Assignee: Toshiba Corp
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Filing: 1983-06-24
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Granted: —
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Expires: 2003-06-24
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Abstract

Abstract PURPOSE:To obtain a rapid semiconductor memory with high capacity by controlling a dynamic memory cell array, a static memory cell line, etc. through a control circuit to be actuated by a control signal. CONSTITUTION:When a line address strobe RAS' to be impressed to the control circuit 130 is turned to the high level, the circuit 130 controls a precharge circuit 10 relating to a dynamic memory, a sense amplifier circuit 20, a dummy cell 30, the dynamic memory cell array 40, a transfer gate circuit 50, etc. at the prescribed timing. During the period that a signal multi-RAS is in the low level, the circuit 130 controls the static memory cell line 60 independently at the prescribed timing and also controls the refresh of the array 40. Thus, the semiconductor memory is made high capacity and high speed by using both the high capacity dynamic memory and the high speed static memory.

Inventors

  • 👤 Yukimasa Uchida
  • 👤 内田 幸正

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 16:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/106; G11C11/00; G11C11/005; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/1078; G11C7/1087

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