Address buffer circuit

Abstract

Abstract PURPOSE:To attain a high-speed operation and the increment of an action margin for an address buffer circuit by changing a reference voltage to be compared with an external input signal to set at a level lower than an initial set value when an input signal is set at a high level and then changed to a level above the initial set value with the input signal at a low level respectively. CONSTITUTION:When an external address input Ai is supplied at a high level, an RAS1 is activated and the levels of nodes N11 and N12 are changed by the levels of Q31 and Q51. Then the comparison voltage Aref' is set at a level higher than the external address and therefore starts reduction at the initial level. Therefore the level of the Q51 is reduced below the level decided by the division of resistance, and the difference of the levels is increased between the Q31 and Q51. Thus the nodes N11 and N21 of a flip-flop are set at high and low levels respectively. On the contrary, the voltage Aref' is increased above the initial level decided by the division of resistance and then above the level of the Q51 to decide a high speed. Then the with the nodes N11 and N21, the low and high level with the N11 and N12 respectively.

Inventors

• 👤 Hidemori Inukai
• 👤 犬飼　英守

Bibliographic Details