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JPS6074074A Expired / Lapsed JP ⏱️ 0.0 years remaining

Priority control system

Assignee: Fujitsu Ltd
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Filing: 1983-09-30
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Granted: —
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Expires: 2003-09-30
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Abstract

Abstract PURPOSE:To improve processing performance by adding a priority to a request inputted to a buffer memory in addition to the priority of a system. CONSTITUTION:Requests A and B inputted from systems A and B are stored in buffer memories A and B through paths 21-1 and 22-1. Request numbers from a counter 15 for request numbers are added to data on those requests when those requests are stored. When a processing part 14 gets ready to accept a new request input, an indication is inputted to a priority circuit 13 through a path 14-2 and also inputted to a readout counter 16. The readout counter 16 sends the next request number following requests which are processed so far by the priority circuit 13 to comparing circuits 17 and 18 according to the indication of the processing part 14, and they are compared with request numbers read out of the buffer memories A and B on FIFO basis to confirm coincidences of the numbers, thereby inputting comparison output signals CMPA and CMPB to the priority circuit 13.

Inventors

  • 👤 Kiyoshi Kawanishi
  • 👤 清 川西

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-07 08:23
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14

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